#ifndef __ASM_ARCH_HL_H
#define __ASM_ARCH_HL_H

#include <linux/init.h>

#define SRAM_GRANULARITY		32
#define SRAM_SIZE			(SZ_128K+SZ_8K)


#define RAM_BASE			(0x10000000)
#define DDR_BASE			(0xA0000000)
#define GICD_REG_BASE		(0x30001000)
#define GICC_REG_BASE		(0x30002000)

#define PMU_REG_BASE			(0xF0000000)
#define TIMER_REG_BASE			(0xF0C00000)
#define GPIO0_REG_BASE			(0xF0300000)
#define GPIO1_REG_BASE			(0xF4000000)
#define UART0_REG_BASE			(0xF0700000)
#define UART1_REG_BASE			(0xF0800000)
#define SPI0_REG_BASE			(0xF0500000)
#define SPI1_REG_BASE			(0xF0600000)
#define SPI2_REG_BASE			(0xF0640000)
#define INTC_REG_BASE			(0xE0200000)
#define GMAC_REG_BASE			(0xE0600000)
#define USBC_REG_BASE			(0xE0700000)
#define DMAC_REG_BASE			(0xE0300000)
#define I2C1_REG_BASE			(0xF0B00000)
#define I2C0_REG_BASE			(0xF0200000)
#define I2C2_REG_BASE			(0xF0100000)
#define SDC0_REG_BASE			(0xE2000000)
#define SDC1_REG_BASE			(0xE2200000)
#define WDT_REG_BASE			(0xF0D00000)
#define PWM_REG_BASE			(0xF0400000)
#define I2S_REG_BASE			(0xF0900000)
#define ACW_REG_BASE			(0xF0A00000)
#define UART2_REG_BASE			(0xF1300000)
#define SADC_REG_BASE			(0xF1200000)
#define EFUSE_REG_BASE			(0xF1600000)
#define AES_REG_BASE			(0xE8200000)
#define RTC_REG_BASE			(0xF1500000)
#define DDRC_REG_BASE			(0xED000000)
#define SMT0_REG_BASE			(0xF0E00000)
#define SMT1_REG_BASE			(0xF0F00000)
#define REG_EPHY_BASE			(0xf1800000)
#define REG_MDIO_BASE			(REG_EPHY_BASE + 0x600)
#define CONSOLE_REG_BASE		UART0_REG_BASE
#define FH_UART_NUMBER			3


#define FH_PMU_REG_SIZE                  0x2114
#define REG_PMU_CHIP_ID                  (0x0000)
#define REG_PMU_IP_VER                   (0x0004)
#define REG_PMU_FW_VER                   (0x0008)
#define REG_PMU_CLK_SEL                  (0x000c)
/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */
#define REG_PMU_SYS_CTRL                 (0x000c)
#define REG_PMU_PLL0                     (0x0010)
#define REG_PMU_PLL1                     (0x0014)
#define REG_PMU_PLL0_CTRL                (0x0018)
#define REG_PMU_CLK_GATE                 (0x001c)
#define REG_PMU_CLK_GATE1                (0x0020)
#define REG_PMU_CLK_DIV0                 (0x0024)
#define REG_PMU_CLK_DIV1                 (0x0028)
#define REG_PMU_CLK_DIV2                 (0x002c)
#define REG_PMU_CLK_DIV3                 (0x0030)
#define REG_PMU_CLK_DIV4                 (0x0034)
#define REG_PMU_CLK_DIV5                 (0x0038)
#define REG_PMU_CLK_DIV6                 (0x003c)
#define REG_PMU_SWRST_MAIN_CTRL          (0x0040)
#define REG_PMU_SWRST_MAIN_CTRL1         (0x0044)
#define REG_PMU_SWRST_AHB_CTRL           (0x0048)
#define REG_PMU_SWRST_APB_CTRL           (0x004c)
#define REG_PMU_SPC_IO_STATUS            (0x0054)
#define REG_PMU_SPC_FUN                  (0x0058)
#define REG_PMU_CLK_DIV7                 (0x005c)
#define REG_PMU_CLK_DIV8                 (0x0060)
#define REG_PMU_PLL1_CTRL                (0x0064)
#define REG_PMU_PAD_POWER_SEL            (0x0074)
#define REG_PMU_SWRSTN_NSR               (0x0078)
#define REG_PMU_SWRSTN_NSR1              (0x007c)
#define REG_PMU_ETHPHY_REG0              (0x2108)
#define REG_PMU_ETHPHY_REG1              (0x210C)

#define REG_PMU_PAD_BOOT_MODE_CFG        (0x0080)
#define REG_PMU_PAD_BOOT_SEL1_CFG        (0x0084)
#define REG_PMU_PAD_BOOT_SEL0_CFG        (0x0088)
#define REG_PMU_PAD_UART0_TX_CFG         (0x008c)
#define REG_PMU_PAD_UART0_RX_CFG         (0x0090)
#define REG_PMU_PAD_I2C0_SCL_CFG         (0x0094)
#define REG_PMU_PAD_I2C0_SDA_CFG         (0x0098)
#define REG_PMU_PAD_SENSOR_CLK_0_CFG     (0x009c)
#define REG_PMU_PAD_SENSOR_RSTN_0_CFG    (0x00a0)
#define REG_PMU_PAD_SENSOR_CLK_1_CFG     (0x00a4)
#define REG_PMU_PAD_SENSOR_RSTN_1_CFG    (0x00a8)
#define REG_PMU_PAD_UART1_TX_CFG         (0x00ac)
#define REG_PMU_PAD_UART1_RX_CFG         (0x00b0)
#define REG_PMU_PAD_I2C1_SCL_CFG         (0x00b4)
#define REG_PMU_PAD_I2C1_SDA_CFG         (0x00b8)
#define REG_PMU_PAD_UART2_TX_CFG         (0x00bc)
#define REG_PMU_PAD_UART2_RX_CFG         (0x00c0)
#define REG_PMU_PAD_USB_PWREN_CFG        (0x00c4)
#define REG_PMU_PAD_PWM0_CFG             (0x00c8)
#define REG_PMU_PAD_PWM1_CFG             (0x00cc)
#define REG_PMU_PAD_GPIO_0_CFG           (0x00d0)
#define REG_PMU_PAD_GPIO_1_CFG           (0x00d4)
#define REG_PMU_PAD_GPIO_2_CFG           (0x00d8)
#define REG_PMU_PAD_GPIO_3_CFG           (0x00dc)
#define REG_PMU_PAD_GPIO_4_CFG           (0x00e0)
#define REG_PMU_PAD_SSI0_CLK_CFG         (0x00e4)
#define REG_PMU_PAD_SSI0_CSN_0_CFG       (0x00e8)
#define REG_PMU_PAD_SSI0_TXD_CFG         (0x00ec)
#define REG_PMU_PAD_SSI0_RXD_CFG         (0x00f0)
#define REG_PMU_PAD_SSI0_D2_CFG          (0x00f4)
#define REG_PMU_PAD_SSI0_D3_CFG          (0x00f8)
#define REG_PMU_PAD_SD0_CD_CFG           (0x00fc)
#define REG_PMU_PAD_SD0_CLK_CFG          (0x0100)
#define REG_PMU_PAD_SD0_CMD_RSP_CFG      (0x0104)
#define REG_PMU_PAD_SD0_DATA_0_CFG       (0x0108)
#define REG_PMU_PAD_SD0_DATA_1_CFG       (0x010c)
#define REG_PMU_PAD_SD0_DATA_2_CFG       (0x0110)
#define REG_PMU_PAD_SD0_DATA_3_CFG       (0x0114)
#define REG_PMU_PAD_SADC_XAIN0_CFG       (0x0118)
#define REG_PMU_PAD_SADC_XAIN1_CFG       (0x011c)
#define REG_PMU_PAD_GPIO_28_CFG          (0x0120)
#define REG_PMU_PAD_GPIO_29_CFG          (0x0124)
#define REG_PMU_PAD_CIS_HSYNC_CFG        (0x0140)
#define REG_PMU_PAD_CIS_VSYNC_CFG        (0x0144)
#define REG_PMU_PAD_CIS_PCLK_CFG         (0x0148)
#define REG_PMU_PAD_CIS_D_0_CFG          (0x014c)
#define REG_PMU_PAD_CIS_D_1_CFG          (0x0150)
#define REG_PMU_PAD_CIS_D_2_CFG          (0x0154)
#define REG_PMU_PAD_CIS_D_3_CFG          (0x0158)
#define REG_PMU_PAD_CKP_MIPI_CFG         (0x0128)
#define REG_PMU_PAD_CKN_MIPI_CFG         (0x012c)
#define REG_PMU_PAD_DN0_MIPI_CFG         (0x0130)
#define REG_PMU_PAD_DP0_MIPI_CFG         (0x0134)
#define REG_PMU_PAD_DN1_MIPI_CFG         (0x0138)
#define REG_PMU_PAD_DP1_MIPI_CFG         (0x013c)
#define REG_PMU_VEU_INT_MASK             (0x01d4)
#define REG_PMU_VEU_INT_RAWSTAT          (0x01d8)
#define REG_PMU_VEU_INT_STAT             (0x01dc)
#define REG_PMU_ARM_INT_MASK             (0x01e0)
#define REG_PMU_ARM_INT_RAWSTAT          (0x01e4)
#define REG_PMU_ARM_INT_STAT             (0x01e8)
#define REG_PMU_A625_INT_MASK            (0x01ec)
#define REG_PMU_A625_INT_RAWSTAT         (0x01f0)
#define REG_PMU_A625_INT_STAT            (0x01f4)
#define REG_PMU_DMA_SEL                  (0x01f8)
#define REG_PMU_WDT_CTRL                 (0x01fc)
#define REG_PMU_DBG_STAT0                (0x0200)
#define REG_PMU_DBG_STAT1                (0x0204)
#define REG_PMU_USB_CFG                  (0x214)
#define REG_PMU_USB_SYS                  (0x210)
#define REG_PMU_USB_SYS1                 (0x228)
#define REG_PMU_USB_TUNE                 (0x218)
#define REG_PMU_PTSLO                    (0x022c)
#define REG_PMU_PTSHI                    (0x0230)
#define REG_PMU_PMU_USER0                (0x0234)
#define REG_PMU_HPROT_CTRL               (0x0238)
#define REG_PMU_QOS_CTRL0                (0x023c)
#define REG_PMU_QOS_CTRL1                (0x0240)
#define REG_PMU_LPC_CTRL0                (0x0300)
#define REG_PMU_LPC_CTRL1                (0x0304)
#define REG_PMU_LPC_CTRL2                (0x0308)
#define REG_PMU_LPC_CTRL3                (0x030c)
#define REG_PMU_LPC_CTRL4                (0x0320)
#define REG_PMU_LPC_CTRL5                (0x0324)
#define REG_PMU_LPC_CTRL6                (0x0328)
#define REG_PMU_WREN                     (0x032c)
#define REG_PMU_BOOT_MODE                (0x0330)
#define REG_PMU_DDR_SIZE                 (0x0334)
#define REG_PMU_RESERVED2                (0x0338)
#define REG_PMU_CHIP_INFO                (0x033c)
#define REG_PMU_EPHY_PARAM               (0x0340)
#define REG_PMU_RTC_PARAM                (0x0344)
#define REG_PMU_DFI_MONITOR_MAP1         (0x0370)
#define REG_PMU_DFI_MONITOR_MAP2         (0x0374)
#define REG_PMU_DFI_MONITOR_MAP3         (0x0378)
#define REG_PMU_DFI_MONITOR_MAP4         (0x037c)
#define REG_PMU_SD1_FUNC_SEL             (0x0380)
#define REG_PMU_PRDCID_CTRL0             (0x0500)
#define REG_PMU_PRDCID_CTRL1             (0x0504)
#define REG_PMU_A625BOOT0                (0x2000)
#define REG_PMU_A625BOOT1                (0x2004)
#define REG_PMU_A625BOOT2                (0x2008)
#define REG_PMU_A625BOOT3                (0x200c)
#define REG_PMU_A625_START_CTRL          (0x2010)
#define REG_PMU_ARC_INTC_MASK            (0x2014)
#define REG_PMU_PERF_MONI_REG0           (0x2018)
#define REG_PMU_PERF_MONI_REG1           (0x201c)
#define REG_PMU_PERF_MONI_REG2           (0x2020)
#define REG_PMU_PERF_MONI_REG3           (0x2024)
#define REG_PMU_PERF_MONI_REG4           (0x2028)
#define REG_PMU_PERF_MONI_REG5           (0x202c)
#define REG_PMU_PERF_MONI_REG6           (0x2030)
#define REG_PMU_PERF_MONI_REG7           (0x2034)
#define REG_PMU_PERF_MONI_REG8           (0x2038)
#define REG_PMU_PERF_MONI_REG9           (0x203c)
#define REG_PMU_PERF_MONI_REG10          (0x2040)
#define REG_PMU_PERF_MONI_REG11          (0x2044)
#define REG_PMU_PERF_MONI_REG12          (0x2048)
#define REG_PMU_PERF_MONI_REG13          (0x204c)
#define REG_PMU_PERF_MONI_REG14          (0x2050)
#define REG_PMU_PERF_MONI_REG15          (0x2054)
#define REG_PMU_PERF_MONI_REG16          (0x2058)
#define REG_PMU_PERF_MONI_REG17          (0x205c)
#define REG_PMU_PERF_MONI_REG18          (0x2060)
#define REG_PMU_PERF_MONI_REG19          (0x2064)
#define REG_PMU_PERF_MONI_REG20          (0x2068)
#define REG_PMU_PERF_MONI_REG21          (0x206c)
#define REG_PMU_PERF_MONI_REG22          (0x2070)
#define REG_PMU_PERF_MONI_REG23          (0x2074)
#define REG_PMU_PERF_MONI_REG24          (0x2078)
#define REG_PMU_PERF_MONI_REG25          (0x207c)
#define REG_PMU_PERF_MONI_REG26          (0x2080)
#define REG_PMU_PERF_MONI_REG27          (0x2084)
#define REG_PMU_PERF_MONI_REG28          (0x2088)
#define REG_PMU_PERF_MONI_REG29          (0x208c)
#define REG_PMU_PERF_MONI_REG30          (0x2090)
#define REG_PMU_PERF_MONI_REG31          (0x2094)
#define REG_PMU_PERF_MONI_REG32          (0x2098)
#define REG_PMU_PERF_MONI_REG33          (0x209c)
#define REG_PMU_PERF_MONI_REG34          (0x20a0)
#define REG_PMU_PERF_MONI_REG35          (0x20a4)
#define REG_PMU_PERF_MONI_REG36          (0x20a8)
#define REG_PMU_PERF_MONI_REG37          (0x20ac)
#define REG_PMU_PERF_MONI_REG38          (0x20b0)
#define REG_PMU_PERF_MONI_REG39          (0x20b4)
#define REG_PMU_PERF_MONI_REG40          (0x20b8)
#define REG_PMU_PERF_MONI_REG41          (0x20bc)
#define REG_PMU_PERF_MONI_REG42          (0x20c0)
#define REG_PMU_PERF_MONI_REG43          (0x20c4)
#define REG_PMU_PERF_MONI_REG44          (0x20c8)
#define REG_PMU_PERF_MONI_REG45          (0x20cc)
#define REG_PMU_PERF_MONI_REG46          (0x20d0)
#define REG_PMU_PERF_MONI_REG47          (0x20d4)
#define REG_PMU_PERF_MONI_REG48          (0x20d8)
#define REG_PMU_PERF_MONI_REG49          (0x20dc)
#define REG_PMU_PERF_MONI_REG50          (0x20e0)
#define REG_PMU_PERF_MONI_REG51          (0x20e4)
#define REG_PMU_PERF_MONI_REG52          (0x20e8)
#define REG_PMU_PERF_MONI_REG53          (0x20ec)
#define REG_PMU_PERF_MONI_REG54          (0x20f0)
#define REG_PMU_PERF_MONI_REG55          (0x20f4)
#define REG_PMU_PERF_MONI_REG56          (0x20f8)
#define REG_PMU_PERF_MONI_REG57          (0x20fc)
#define REG_PMU_PERF_MONI_REG58          (0x2100)
#define REG_PMU_PERF_MONI_REG59          (0x2104)
#define REG_PMU_MIPI_TEST_CTRL_REG       (0x2108)
#define REG_PMU_EFHY_REG0                (0x210c)
#define REG_PMU_EFHY_REG1                (0x2110)

#define FH_GMAC_AHB_RESET					(1<<17)
#define FH_GMAC_SPEED_100M					(1<<24)
#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL)
#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG)
#define PMU_RXDV_GPIO_MASK (0x0f000000)
#define PMU_RXDV_GPIO_VAL (0x01000000)

#define PMU_DWI2S_CLK_SEL_REG   (REG_PMU_CLK_SEL)
#define PMU_DWI2S_CLK_SEL_SHIFT (1)
#define PMU_DWI2S_CLK_DIV_REG   (REG_PMU_CLK_DIV6)
#define PMU_DWI2S_CLK_DIV_SHIFT (0)

/*ATTENTION: written by ARC */
#define PMU_ARM_INT_MASK             (0x01ec)
#define PMU_ARM_INT_RAWSTAT          (0x01f0)
#define PMU_ARM_INT_STAT             (0x01f4)

#define PMU_A625_INT_MASK             (0x01e0)
#define PMU_A625_INT_RAWSTAT          (0x01e4)
#define PMU_A625_INT_STAT             (0x01e8)

#define PMU_IRQ			(0 + 32)
#define DDRC_IRQ		(1 + 32)
#define WDT_IRQ			(2 + 32)
#define TMR0_IRQ		(3 + 32)
#define VEU_IRQ0		(4 + 32)
#define VEU_IRQ1		(5 + 32)
#define VEU_IRQ2		(6 + 32)
#define PERF_IRQ		(8 + 32)
#define VEU_SW_IRQ		(9 + 32)
#define NN_IRQ			(10 + 32)
#define I2C0_IRQ		(11 + 32)
#define I2C1_IRQ		(12 + 32)
#define JPEG_IRQ		(13 + 32)
#define BGM_IRQ			(14 + 32)
#define VEU_LOOP_IRQ	(15 + 32)
#define AES_IRQ			(16 + 32)
#define MIPIC_IRQ		(17 + 32)
#define MIPI_WRAP_IRQ	(18 + 32)
#define ACW_IRQ			(19 + 32)
#define SADC_IRQ		(20 + 32)
#define SPI1_IRQ		(21 + 32)
#define JPEG_LOOP_IRQ	(22 + 32)
#define DMAC0_IRQ		(23 + 32)
#define DMAC1_IRQ		(24 + 32)
#define GPIO0_IRQ		(26 + 32)
#define SPI0_IRQ		(28 + 32)
#define ARC_SW_IRQ		(29 + 32)
#define UART0_IRQ		(30 + 32)
#define UART1_IRQ		(31 + 32)
#define ARM_SW_IRQ		(32 + 32)
#define RTC_IRQ			(33 + 32)
#define SMT0_IRQ		(34 + 32)
#define SMT1_IRQ		(35 + 32)
#define PWM_IRQ			(36 + 32)
#define SPI2_IRQ		(38 + 32)
#define USBC_IRQ		(39 + 32)
#define GPIO1_IRQ		(40 + 32)
#define UART2_IRQ		(41 + 32)
#define SDC0_IRQ		(42 + 32)
#define SDC1_IRQ		(43 + 32)
#define GMAC_IRQ		(44 + 32)
#define EPHY_IRQ		(45 + 32)
#define I2C2_IRQ		(46 + 32)
#define RTC_ALM_IRQ		(47 + 32)
#define RTC_CORE_IRQ	(48 + 32)
/* because chips with some same function in different */
/* pmu register, use wrap marco to make code to be same */
#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL)

#define MEM_START_PHY_ADDR	DDR_BASE
#define MEM_SIZE			0x8000000


#define NR_INTERNAL_IRQS	(64)
#define NR_EXTERNAL_IRQS	(64)
/*#define NR_IRQS			(NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/

/* SWRST_MAIN_CTRL */
#define CPU_RSTN_BIT			(0)
#define UTMI_RSTN_BIT			(1)
#define DDRPHY_RSTN_BIT			(2)
#define DDRC_RSTN_BIT			(3)
#define GPIO0_DB_RSTN_BIT		(4)
#define GPIO1_DB_RSTN_BIT		(5)
#define PIXEL_RSTN_BIT			(6)
#define PWM_RSTN_BIT			(7)
#define SPI0_RSTN_BIT			(8)
#define SPI1_RSTN_BIT			(9)
#define I2C0_RSTN_BIT			(10)
#define I2C1_RSTN_BIT			(11)
#define ACODEC_RSTN_BIT			(12)
#define I2C2_RSTN_BIT			(13)
#define UART0_RSTN_BIT			(14)
#define UART1_RSTN_BIT			(15)
#define SADC_RSTN_BIT			(16)
#define ADAPT_RSTN_BIT			(17)
#define TMR_RSTN_BIT			(18)
#define UART2_RSTN_BIT			(19)
#define SPI2_RSTN_BIT			(20)
#define JPEG_ADAPT_RSTN_BIT		(21)
#define ARC_RSTN_BIT			(22)
#define EFUSE_RSTN_BIT			(23)
#define JPEG_RSTN_BIT			(24)
#define VEU_RSTN_BIT			(25)
#define NN_RSTN_BIT				(26)
#define ISP_RSTN_BIT			(27)
#define BGM_RSTN_BIT			(28)
#define PTS_RSTN_BIT			(29)
#define EPHY_RSTN_BIT			(30)
#define SYS_RSTN_BIT			(31)

/* SWRST_AHB_CTRL */
#define EMC_HRSTN_BIT			(0)
#define SDC1_HRSTN_BIT			(1)
#define SDC0_HRSTN_BIT			(2)
#define AES_HRSTN_BIT			(3)
#define DMAC0_HRSTN_BIT			(4)
#define INTC_HRSTN_BIT			(5)
#define JEPG_HRSTN_BIT			(6)
#define JEPG_ADAPT_HRSTN_BIT	(7)
#define VEU_HRSTN_BIT			(8)
#define VEU_ADAPT_HRSTN_BIT		(9)
#define NN_HRSTN_BIT			(10)
#define ISP_HRSTN_BIT			(11)
#define USB_HRSTN_BIT			(12)
#define HRSTN_BIT				(13)
#define EMAC_HRSTN_BIT			(17)
#define DDRC_HRSTN_BIT			(19)
#define ADAPT_HRSTN_BIT			(21)


/* SWRST_APB_CTRL */
#define ACODEC_PRSTN_BIT		(0)
#define UART1_PRSTN_BIT			(2)
#define UART0_PRSTN_BIT			(3)
#define SPI0_PRSTN_BIT			(4)
#define SPI1_PRSTN_BIT			(5)
#define GPIO0_PRSTN_BIT			(6)
#define UART2_PRSTN_BIT			(7)
#define I2C2_PRSTN_BIT			(8)
#define I2C0_PRSTN_BIT			(9)
#define I2C1_PRSTN_BIT			(10)
#define TMR_PRSTN_BIT			(11)
#define PWM_PRSTN_BIT			(12)
#define MIPIW_PRSTN_BIT			(13)
#define MIPIC_PRSTN_BIT			(14)
#define RTC_PRSTN_BIT			(15)
#define SADC_PRSTN_BIT      	(16)
#define EFUSE_PRSTN_BIT			(17)
#define SPI2_PRSTN_BIT      	(18)
#define WDT_PRSTN_BIT      	    (19)
#define GPIO1_PRSTN_BIT			(20)

/* timer clk  fpga 1M,soc 50M*/
#ifdef CONFIG_FPGA
#define TIMER_CLK			(1000000)
#else
#define TIMER_CLK			(50000000)
#endif

#define UART1_TX_HW_HANDSHAKE   (9)
#define UART1_RX_HW_HANDSHAKE   (8)
#define UART2_TX_HW_HANDSHAKE   (13)
#define UART2_RX_HW_HANDSHAKE   (12)
#define UART1_DMA_TX_CHAN       (4)
#define UART1_DMA_RX_CHAN       (5)
#define UART2_DMA_TX_CHAN       (4)
#define UART2_DMA_RX_CHAN       (5)

/*sdio*/
#define SIMPLE_0     (0)
#define SIMPLE_22    (1)
#define SIMPLE_45    (2)
#define SIMPLE_67    (3)
#define SIMPLE_90    (4)
#define SIMPLE_112   (5)
#define SIMPLE_135   (6)
#define SIMPLE_157   (7)
#define SIMPLE_180   (8)
#define SIMPLE_202   (9)
#define SIMPLE_225   (10)
#define SIMPLE_247   (11)
#define SIMPLE_270   (12)
#define SIMPLE_292   (13)
#define SIMPLE_315   (14)
#define SIMPLE_337   (15)



#define SDIO0_RST_BIT       (~UL(1<<2))
#define SDIO0_CLK_RATE      (50000000)
#define SDIO0_CLK_DRV_SHIFT (20)
#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO0_CLK_SAM_SHIFT (16)
#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0)


#define SDIO1_RST_BIT       (~UL(1<<1))
#define SDIO1_CLK_RATE      (50000000)
#define SDIO1_CLK_DRV_SHIFT (12)
#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO1_CLK_SAM_SHIFT (8)
#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0)

#define SDC0_HRSTN  (0x1<<2)
#define SDC1_HRSTN  (0x1<<1)
#define SDC2_HRSTN  (0)


/*usb*/
#define IRQ_UHOST          USBC_IRQ
#define FH_PA_OTG          USBC_REG_BASE
#define IRQ_OTG            IRQ_UHOST
#define FH_SZ_USBHOST	   SZ_1M
#define FH_SZ_OTG          SZ_1M

#define USB_UTMI_RST_BIT      (0x1<<1)
#define USB_PHY_RST_BIT       (0x11)
#define USB_SLEEP_MODE_BIT    (0x1<<24)
#define USB_IDDQ_PWR_BIT    (0x1<<10)
#define USB_TUNE_ADJ_SET	(0x78203344)


/* Specific Uart Number */
#define FH_UART_NUMBER 3
#define CLK_SCAN_BIT_POS                (28)
#define INSIDE_PHY_ENABLE_BIT_POS       (24)
#define MAC_REF_CLK_DIV_MASK            (0x0f)
#define MAC_REF_CLK_DIV_BIT_POS         (24)
#define MAC_PAD_RMII_CLK_MASK           (0x0f)
#define MAC_PAD_RMII_CLK_BIT_POS        (24)
#define MAC_PAD_MAC_REF_CLK_BIT_POS     (28)
#define ETH_REF_CLK_OUT_GATE_BIT_POS    (25)
#define ETH_RMII_CLK_OUT_GATE_BIT_POS   (28)
#define IN_OR_OUT_PHY_SEL_BIT_POS       (26)
#define INSIDE_CLK_GATE_BIT_POS         (0)
#define INSIDE_PHY_SHUTDOWN_BIT_POS     (31)
#define INSIDE_PHY_RST_BIT_POS          (30)
#define INSIDE_PHY_TRAINING_BIT_POS     (27)
#define INSIDE_PHY_TRAINING_MASK        (0x0f)

#define DMA_FIXED_CHANNEL_NUM       6

#define TRAINING_EFUSE_ACTIVE_BIT_POS          4
#define EPHY_PASS_CHECK_BIT_POS          0

#define SD1_FUNC_SEL_MAP    {1, 0, 2}

#endif /* __ASM_ARCH_HL_H */
